Wafer carrier having thermal cover for chemical vapor deposition systems

ABSTRACT

The invention relates generally to semiconductor fabrication technology and, more particularly, to chemical vapor deposition (CVD) processing and associated apparatus for addressing temperature non-uniformities on semiconductor wafer surfaces. Embodiments include a wafer carrier for use in a system for growing epitaxial layers on one or more wafers by CVD, the wafer carrier comprising a top plate and base plate which function coordinately to reduce temperature variability caused during CVD processing.

PRIOR APPLICATION

This Application claims priority to U.S. Provisional Application No.61/920,943 filed Dec. 26, 2013, the content of which is incorporated byreference herein.

FIELD OF THE INVENTION

The invention relates generally to semiconductor fabrication technologyand, more particularly, to chemical vapor deposition (CVD) processingand associated apparatus having features for reducing temperaturenon-uniformities on semiconductor wafer surfaces.

BACKGROUND OF THE INVENTION

In the fabrication of light-emitting diodes (LEDs) and otherhigh-performance devices such as laser diodes, optical detectors, andfield effect transistors, a chemical vapor deposition (CVD) process istypically used to grow a thin film stack structure using materials suchas gallium nitride over a sapphire or silicon substrate. A CVD toolincludes a process chamber, which is a sealed environment that allowsinfused gases to be deposited upon the substrate (typically in the formof wafers) to grow the thin film layers. An example of a current productline of such manufacturing equipment is the TurboDisc® family of metalorganic chemical vapor deposition (MOCVD) systems, manufactured by VeecoInstruments Inc. of Plainview, N.Y.

A number of process parameters are controlled, such as temperature,pressure, and gas flow rate, to achieve a desired crystal growth.Different layers are grown using varying materials and processparameters. For example, devices formed from compound semiconductorssuch as III-V semiconductors are typically formed by growing successivelayers of the compound semiconductor using MOCVD. In this process, thewafers are exposed to a combination of gases, including a metal organiccompound as a source of a group III metal, and also including a sourceof a group V element which flow over the surface of the wafer while thewafer is maintained at an elevated temperature. Generally, the metalorganic compound and group V source are combined with a carrier gas,which does not participate appreciably in the reaction as, for example,nitrogen. One example of a III-V semiconductor is gallium nitride, whichcan be formed by reaction of an organo-gallium compound and ammonia on asubstrate having a suitable crystal lattice spacing, as for example, asapphire wafer. The wafer is usually maintained at a temperature on theorder of 1000-1100° C. during deposition of gallium nitride and relatedcompounds.

In MOCVD processing, where the growth of crystals occurs by chemicalreaction on the surface of the substrate, the process parameters must betightly controlled to ensure that the chemical reaction proceeds underthe required conditions. Even small variations in process conditions canadversely affect device quality and production yield. For instance, if agallium and indium nitride layer is deposited, variations in wafersurface temperature will cause variations in the composition and bandgapof the deposited layer. Because indium has a relatively high vaporpressure, the deposited layer will have a lower proportion of indium anda greater bandgap in those regions of the wafer where the surfacetemperature is higher. If the deposited layer is an active,light-emitting layer of an LED structure, the emission wavelength of theLEDs formed from the wafer will also vary to an unacceptable degree.

In an MOCVD processing chamber, semiconductor wafers on which layers ofthin film are to be grown are placed on rapidly-rotating carousels,referred to as wafer carriers, to provide a uniform exposure of theirsurfaces to the atmosphere within the reactor chamber for the depositionof the semiconductor materials. Rotation speed is on the order of 1,000RPM. The wafer carriers are typically machined out of a highly thermallyconductive material such as graphite, and are often coated with aprotective layer of a material such as silicon carbide. Each wafercarrier has a set of circular indentations, or pockets, in its topsurface in which individual wafers are placed. Typically, the wafers aresupported in spaced relationship to the bottom surface of each of thepockets to permit the flow of gas around the edges of the wafer. Someexamples of pertinent technology are described in U.S. PatentApplication Publication No. 2012/0040097, U.S. Pat. Nos. 8,092,599,8,021,487, U.S. Patent Application Publication No. 2007/0186853, U.S.Pat. Nos. 6,902,623, 6,506,252, and 6,492,625, the disclosures of whichare incorporated by reference herein.

The wafer carrier is supported on a spindle within the reaction chamberso that the top surface of the wafer carrier having the exposed surfacesof the wafers faces upwardly toward a gas distribution device. While thespindle is rotated, the gas is directed downwardly onto the top surfaceof the wafer carrier and flows across the top surface toward theperiphery of the wafer carrier. The used gas is evacuated from thereaction chamber through ports disposed below the wafer carrier. Thewafer carrier is maintained at the desired elevated temperature byheating elements, typically electrical resistive heating elementsdisposed below the bottom surface of the wafer carrier. These heatingelements are maintained at a temperature above the desired temperatureof the wafer surfaces, whereas the gas distribution device typically ismaintained at a temperature well below the desired reaction temperatureso as to prevent premature reaction of the gases. Therefore, heat istransferred from the heating elements to the bottom surface of the wafercarrier and flows upwardly through the wafer carrier to the individualwafers. The gas flow over the wafers varies depending on the radialposition of each wafer, with outermost-positioned wafers being subjectedto higher flow rates due to their faster velocity during rotation. Eveneach individual wafer can have temperature non-uniformities, i.e., coldspots and hot spots depending upon its geometrical position relative tothe other wafers on the carrier.

During MOCVD processing, the wafer carrier is predominantly heated byradiation, with the radiant energy impinging on the bottom of thecarrier. For example, a cold-wall CVD reactor design (i.e., one thatuses non-isothermal heating from the bottom) creates conditions in thereaction chamber where a top surface of the wafer carrier is cooler thanthe bottom surface. The degree of radiative emission from the wafercarrier is determined by the emissivity of the carrier and thesurrounding components. Changing the interior components of the reactionchamber such as the cold-plate, confined inlet flange, shutter, andother regions, to a higher emissivity material can result in increasedradiative heat transfer. Likewise, reducing the emissivity of thecarrier will result in less radiative heat removal from the carrier. Thedegree of convective cooling of the carrier surface is driven by theoverall gas flow pumping through the chamber, along with the heatcapacity of the gas mixture (H2, N2, NH3, OMs, etc.). Additionally,introducing a wafer, such as a sapphire wafer, in a pocket can enhancethe transverse component of the thermal streamlines, resulting in a“blanketing” effect. This phenomenon results in a radial thermal profileat the pocket floor that is hotter in the center and lower towards theouter radius of the pocket.

This non-uniform temperature profile on the surface of the wafer, whichis compounded by centripetal forces during rotation (i.e., the“proximity” effect), can significantly decrease semiconductor productionyield. Thus, a great deal of effort has been devoted to designing asystem with features to minimize temperature variations duringprocessing. Given the extreme conditions wafers are subject to duringMOCVD processing, and the impact these conditions have on productionyield, there remains a need for improved technologies to further reducetemperature non-uniformities.

SUMMARY OF THE INVENTION

Aspects of the invention are directed to a chemical vapor deposition(CVD) system in which temperature non-uniformities on the surfaces ofsemiconductor wafers are significantly reduced. In one aspect, a wafercarrier has a body formed symmetrically about a central axis, andincluding a generally planar top surface that is situatedperpendicularly to the central axis. A plurality of wafer retentionpockets are recessed in the body from the top surface. Each of the waferretention pockets includes a floor surface generally parallel to the topsurface; and a peripheral wall surface surrounding the floor surface anddefining a periphery of that wafer retention pocket. Each waferretention pocket has a pocket center situated along a correspondingwafer carrier radial axis that is perpendicular to the central axis.

In various embodiments, a wafer carrier for use in a system for growingepitaxial layers on one or more wafers by CVD can comprise a top plateand a base plate, wherein the top plate covers the areas of the baseplate not covered by one or more wafers, and wherein the presence of thetop plate reduces temperature variability during CVD processing. The topplate can comprise the same material as the plurality of wafers, forexample, silicon or sapphire; or the top plate can comprise a similarmaterial as the plurality of wafers, for example, quartz, siliconcarbide, solid silicon carbide, or aluminum nitride. In suchembodiments, the base plate can generally be comprised of either siliconcarbide or silicon carbide coated graphite. In various embodiments,temperature non-uniformities can be reduced when the top plate and theplurality of wafers are in the same horizontal plane within the wafercarrier. In other embodiments, temperature non-uniformities can bereduced when the top plate and the plurality of wafers are the samedistance from the base plate. For example, the wafers and the top plateor top plates can rest on tabs or ring structures extending from thebase plate, such that the gap distance between the wafers and the topsurface of the wafer pocket is the same or similar as the gap distancebetween the top plates and the top surface of the base plate in theregions not occupied by wafers.

In other embodiments, temperature non-uniformities can be reduced whenthe top plate and the plurality of wafers are the same thickness. Forexample, the top plate and the plurality of wafers can be in the samehorizontal plane and be in direct contact, or top plate and theplurality of wafers can be in the same horizontal plane and not indirect contact. In some embodiments, the base plate can comprise thesurface directly beneath the plurality of wafers, or the top plate cancomprise the surface directly underneath the plurality of wafers. Insome embodiments, the base plate can comprise the surface directlybeneath the plurality of wafers and be in direct contact with thewafers, or the top plate can comprise the surface directly underneaththe plurality of wafers and be in direct contact with the wafers. Ingeneral, the greatest reduction in temperature non-uniformities can beobtained when the top plate comprises the same material as the pluralityof wafers, when the top plate and the plurality of wafers are the samevertical distance from the base plate, and when the top plate and theplurality of wafers are the same thickness. However, other embodimentscontemplate varying the material selection between the wafers and thetop plate. Temperature non-uniformities in this case can be reduced withcorresponding variation of relative thickness between the top plate andwafers, relative spacing over the bottom plate between the top plate andwafers, or some combination of these parameters to produce an overallarrangement. Other embodiments include a top plate that is arranged at adifferent vertical spacing relative to the bottom plate than thevertical spacing of the plurality of the wafer relative to the bottomplate.

In some embodiments, the top plate can be comprised of a single piece ofmaterial, or the top plate can be comprised of one or more segments.Regardless, the top plate and the base plate can be fastened together,for example, using staples comprising molybdenum or similar materials.When fastened together, the top plate and the base plate cancoordinately form a wafer pocket shaped from a compound radius of two ormore intersecting arcs, or the top plate and the base plate cancoordinately form a wafer pocket shaped from a compound radius of two ormore non-intersecting arcs. In some embodiments, a wafer carrierconfigured of a top plate and a base plate as described herein canreduce temperature variability during CVD processing by a factor ofabout 2.0, about 2.5, about 3.0, about 3.5, about 4.0, about 4.5, about5.0, about 5.5, about 6.0, about 6.5, about 7.0, about 7.5, about 8.0,about 8.5, about 9.0, about 9.5, or about 10.

Embodiments can also include a method for reducing temperaturenon-uniformities in a system for growing epitaxial layers on one or morewafers by chemical vapor deposition (CVD). The method can compriseassembling a wafer carrier comprising a top plate and a base plate,wherein the top plate covers the areas of the base plate not covered byone or more wafers, and wherein the presence of the top plate reducestemperature variability during CVD processing. The top plate and thebase plate can be configured as described above, with the greatestreduction in temperature non-uniformities obtained when the top platecomprises the same material as the plurality of wafers, when the topplate and the plurality of wafers are the same distance from the baseplate, and when the top plate and the plurality of wafers are the samethickness.

Advantageously, the use of a top plate and a base plate, wherein the topplate covers the areas of the base plate not covered by one or morewafers, as described herein, provides better uniformity in the thermaldistribution on the surface of a wafer subjected to CVD processing. Anumber of other advantages will become apparent from the followingDetailed Description.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be more completely understood in consideration of thefollowing detailed description of various embodiments of the inventionin connection with the accompanying drawings, in which:

FIG. 1 illustrates a chemical vapor deposition apparatus in accordancewith one embodiment of the invention.

FIG. 2 is a perspective view diagram illustrating a wafer carrier usedwith a MOCVD system, according to one embodiment of the invention.

FIG. 3 is a diagram of a cross-sectional view taken along the lineshown, detailing a wafer pocket used with a MOCVD system, according toone embodiment of the invention.

FIG. 4 is a temperature gradient profile, according to one embodiment ofthe invention.

FIGS. 5A through 5E are diagrams of cross-sectional views of a pocket ofa wafer carrier comprising a top plate and a base plate, according toone embodiment of the invention.

FIGS. 6A through 6C are illustrations of a top plate and top platesegments of a wafer carrier, according to one embodiment of theinvention.

FIGS. 7A through 7C are diagrams of cross-sectional views of a pocket ofa wafer carrier comprising a top plate and a base plate, according toone embodiment of the invention.

FIG. 8 illustrates and compares two temperature gradient profilesobtained using gallium nitride (GaN) wafers, according to one embodimentof the invention.

FIGS. 9A and 9B illustrate and compare two temperature gradient profilesobtained using wafers with multiple quantum wells (MQW), according toone embodiment of the invention.

While the invention is amenable to various modifications and alternativeforms, specifics thereof have been shown by way of example in thedrawings and will be described in detail. It should be understood,however, that the intention is not to limit the invention to theparticular embodiments described. On the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

FIG. 1 illustrates a chemical vapor deposition apparatus in accordancewith one embodiment of the invention. Reaction chamber 5 defines aprocess environment space. Gas distribution device 10 is arranged at oneend of the chamber. The end having gas distribution device 10 isreferred to herein as the “top” end of reaction chamber 5. This end ofthe chamber typically, but not necessarily, is disposed at the top ofthe chamber in the normal gravitational frame of reference. Thus, thedownward direction as used herein refers to the direction away from gasdistribution device 10; whereas the upward direction refers to thedirection within the chamber, toward gas distribution device 10,regardless of whether these directions are aligned with thegravitational upward and downward directions. Similarly, the “top” and“bottom” surfaces of elements are described herein with reference to theframe of reference of reaction chamber 5 and gas distribution device 10.

Gas distribution device 10 is connected to sources 15, 20, and 25 forsupplying process gases to be used in the wafer treatment process, suchas a carrier gas and reactant gases, such as a metalorganic compound anda source of a group V metal. Gas distribution device 10 is arranged toreceive the various gases and direct a flow of process gasses generallyin the downward direction. Gas distribution device 10 desirably is alsoconnected to coolant system 30 arranged to circulate a liquid throughgas distribution device 10 so as to maintain the temperature of the gasdistribution device at a desired temperature during operation. A similarcoolant arrangement (not shown) can be provided for cooling the walls ofreaction chamber 5. Reaction chamber 5 is also equipped with exhaustsystem 35 arranged to remove spent gases from the interior of thechamber through ports (not shown) at or near the bottom of the chamberso as to permit continuous flow of gas in the downward direction fromgas distribution device 10.

Spindle 40 is arranged within the chamber so that the central axis 45 ofspindle 40 extends in the upward and downward directions. Spindle 40 ismounted to the chamber by a conventional rotary pass-through device 50incorporating bearings and seals (not shown) so that spindle 40 canrotate about central axis 45, while maintaining a seal between spindle40 and the wall of reaction chamber 5. The spindle has fitting 55 at itstop end, i.e., at the end of the spindle closest to gas distributiondevice 10. As further discussed below, fitting 55 is an example of awafer carrier retention mechanism adapted to releasably engage a wafercarrier. In the particular embodiment depicted, fitting 55 is agenerally frustoconical element tapering toward the top end of thespindle and terminating at a flat top surface. A frustoconical elementis an element having the shape of a frustum of a cone. Spindle 40 isconnected to rotary drive mechanism 60 such as an electric motor drive,which is arranged to rotate spindle 40 about central axis 45.

Heating element 65 is mounted within the chamber and surrounds spindle40 below fitting 55. Reaction chamber 5 is also provided with entryopening 70 leading to antechamber 75, and door 80 for closing andopening the entry opening. Door 80 is depicted only schematically inFIG. 1, and is shown as movable between the closed position shown insolid lines, in which the door isolates the interior of reaction chamber5 from antechamber 75, and an open position shown in broken lines at80′. The door 80 is equipped with an appropriate control and actuationmechanism for moving it between the open position and closed positions.In practice, the door may include a shutter movable in the upward anddownward directions as disclosed, for example, in U.S. Pat. No.7,276,124, the disclosure of which is hereby incorporated by referenceherein. The apparatus depicted in FIG. 1 may further include a loadingmechanism (not shown) capable of moving a wafer carrier from theantechamber 75 into the chamber and engaging the wafer carrier withspindle 40 in the operative condition, and also capable of moving awafer carrier off of spindle 40 and into antechamber 75.

The apparatus also includes a plurality of wafer carriers. In theoperating condition shown in FIG. 1, a first wafer carrier 85 isdisposed inside reaction chamber 5 in an operative position, whereas asecond wafer carrier 90 is disposed within antechamber 75. Each wafercarrier includes body 95 which is substantially in the form of acircular disc having a central axis (See FIG. 2). Body 95 is formedsymmetrically about central axis. In the operative position, the centralaxis of the wafer carrier body is coincident with central axis 45 ofspindle 40. Body 95 may be formed as a single piece or as a composite ofplural pieces. For example, as disclosed in U.S. Patent Application Pub.No. 20090155028, the disclosure of which is hereby incorporated byreference herein, the wafer carrier body may include a hub defining asmall region of the body surrounding the central axis and a largerportion defining the remainder of the disc-like body. Body 95 isdesirably formed from materials which do not contaminate the process andwhich can withstand the temperatures encountered in the process. Forexample, the larger portion of the disc may be formed largely orentirely from materials such as graphite, silicon carbide, or otherrefractory materials. Body 95 generally has a planar top surface 100 anda bottom surface 110 extending generally parallel to one another andgenerally perpendicular to the central axis of the disc. Body 95 alsohas one, or a plurality, of wafer-holding features adapted to hold aplurality of wafers.

In operation, wafer 115, such as a disc-like wafer formed from sapphire,silicon carbide, or other crystalline substrate, is disposed within eachpocket 120 of each wafer carrier. Typically, wafer 115 has a thicknesswhich is small in comparison to the dimensions of its major surfaces.For example, a circular wafer of about 2 inches (50 mm) in diameter maybe about 430 μm thick or less. As illustrated in FIG. 1, wafer 115 isdisposed with a top surface facing upwardly, so that the top surface isexposed at the top of the wafer carrier. It should be noted that invarious embodiments, wafer carrier 85 carries different quantities ofwafers. For instance, in one example embodiment, wafer carrier 85 can beadapted to hold six wafers. In another example embodiment, as shown inFIG. 2, the wafer carrier holds 12 wafers.

In a typical MOCVD process, wafer carrier 85 with wafers loaded thereonis loaded from antechamber 75 into reaction chamber 5 and placed in theoperative position shown in FIG. 1. In this condition, the top surfacesof the wafers face upwardly, towards gas distribution device 10. Heatingelement 65 is actuated, and rotary drive mechanism 60 operates to turnspindle 40 and hence wafer carrier 85 around axis 45. Typically, spindle40 is rotated at a rotational speed from about 50-1500 revolutions perminute. Process gas supply units 15, 20, and 25 are actuated to supplygases through gas distribution device 10. The gases pass downwardlytoward wafer carrier 85, over top surface 100 of wafer carrier 85 andwafers 115, and downwardly around the periphery of the wafer carrier tothe outlet and to exhaust system 50. Thus, the top surface of the wafercarrier and the top surfaces of wafer 115 are exposed to a process gasincluding a mixture of the various gases supplied by the various processgas supply units. Most typically, the process gas at the top surface ispredominantly composed of the carrier gas supplied by carrier gas supplyunit 20. In a typical chemical vapor deposition process, the carrier gasmay be nitrogen, and hence the process gas at the top surface of thewafer carrier is predominantly composed of nitrogen with some amount ofthe reactive gas components.

Heating elements 65 transfer heat to the bottom surface 110 of wafercarrier 85, principally by radiant heat transfer. The heat applied tothe bottom surface of wafer carrier 85 flows upwardly through the body95 of the wafer carrier to the top surface 100 of the wafer carrier.Heat passing upwardly through the body also passes upwardly through gapsto the bottom surface of each wafer, and upwardly through the wafer tothe top surface of wafer 115. Heat is radiated from the top surface 100of wafer carrier 85 and from the top surfaces of the wafer to the colderelements of the process chamber as, for example, to the walls of theprocess chamber and to gas distribution device 10. Heat is alsotransferred from the top surface 100 of wafer carrier 85 and the topsurfaces of the wafers to the process gas passing over these surfaces.

In the embodiment depicted, the system includes a number of featuresdesigned to determine uniformity of heating of the surfaces of eachwafer 115. In this embodiment, temperature profiling system 125 receivestemperature information that can include a temperature and temperaturemonitoring positional information from temperature monitor 130. Inaddition, temperature profiling system 125 receives wafer carrierpositional information, which in one embodiment can come from rotarydrive mechanism 60. With this information, temperature profiling system125 constructs a temperature profile of the wafers 120 on wafer carrier85. The temperature profile represents a thermal distribution on thesurface of each of the wafers 120.

FIGS. 2 and 3 illustrate wafer carrier 200, also referred to as asusceptor, in greater detail. Each wafer retention site is in the formof a generally circular recess, or pocket 205, extending downwardly intobody 210 from the top surface 215. FIG. 3 is a cross-sectional view ofpocket 205 (demarcated with a horizontal line and two angled arrow inFIG. 2). The generally circular shape is made to correspond to the shapeof wafer 240. Each wafer carrier 200 includes body 210 that issubstantially in the form of a circular disc having a central axis 220.Body 210 is formed symmetrically about central axis 220. In theoperative position, the central axis 220 of wafer carrier body 210 iscoincident with the axis of the spindle (See FIG. 3). Body 210 may beformed as a single piece or as a composite of plural pieces. Each pocket205 has a floor surface 225 disposed below the surrounding portions oftop surface 215. Each pocket 205 also has a peripheral wall surface 230surrounding floor surface 225 and defining the periphery of pocket 205.Peripheral wall surface 230 extends downwardly from the top surface 215of body 210 to floor surface 225. In various embodiments, as depicted inparticular in FIG. 3, peripheral wall surface 230 has an undercut wherethe wall slopes inwards, over at least a portion of the periphery. Thus,peripheral wall surface 230 forms an acute angle relative to floorsurface 225. In one example embodiment, the angle formed betweenperipheral wall surface 230 and floor surface 225 is 80 degrees.

In a related embodiment (not shown), portions of peripheral wall surface230 have varying degrees of sloping. For instance, in one suchembodiment, those portions of peripheral wall surface 230 that arefurthest from the central axis 220 of the wafer carrier have a moreacute angle. In another related embodiment, as illustrated in FIG. 3,the pocket floor surface 225 (i.e., the top surface of base plate in thewafer pocket region) includes standoff features, such as tabs 235located in certain locations along the periphery of each pocket 205.Tabs 235 raise wafer 240 off of pocket floor surface 225, therebypermitting some flow of gas around the edges and below the bottomsurface of wafer 240. In other embodiments, wafer 240 can be raised frompocket floor surface 225 using a ring that fits inside pocket 205, justunderneath peripheral wall surface 230; the ring can occupy the positionof tabs 235 (i.e., in lieu of tabs), such that the outer periphery ofwafer 240 rests on the ring.

Generally, wafer retention sites, or pockets, are in the form of acircular recess, extending downwardly into the body of a wafer carrier,as shown above in FIGS. 1-3. In the case of multi-wafer pockets, whichoften times have non-concentric pocket locations, the temperatureprofile (also called a thermal profile; see FIG. 4) is more varied, dueto the gas streamline path passing over both the wafer carrier and waferregions, and the significant centripetal forces involved during waferprocessing. For example, in high-speed rotating disc reactors, the gasstreamlines spiral outward in a generally tangential direction. In oneaspect, as shown in FIG. 4, when the gas streamline is passing overexposed portions 400 (e.g., the area between the wafers) of the wafercarrier, exposed portions 400 are heated up relative to the regionswhere it is passing over the wafers. In general, exposed portions 400are quite hot relative to the other regions of the carrier, as the heatflux streamlines have channeled the streamlines into this region due tothe “blanketing” effect. Thus, the gas paths create a tangentialgradient in temperature due to the convective cooling, which is hotterat the leading edge (entry of the fluid streamline to the wafer)relative to the trailing edge (exit of the fluid streamline over thewafer). As shown in FIG. 4, this can result in significant temperaturenon-uniformities on the surface of the wafer that reduce productionyield. Generally, the center of the wafer surface is relatively hotterthan other portions of the wafer surface due to the “blanketing” effect,as is the outside portion of the periphery of the wafer that contactsthe wafer pocket (subject to centripetal force during rotation), due tothe “proximity” effect (region 405). In contrast, the inside portion ofthe periphery of the wafer that is closest to the axis of rotation ofthe wafer carrier is relatively cooler (region 410).

As an improved structure to maintain a more uniform temperature profileduring MOCVD processing, ultimately reducing temperaturenon-uniformities and increasing production yield, wafer carriersaccording to embodiments of the invention are constructed to receive aplurality of individual top plates, each of which is sized and shaped tocover a corresponding portion of the top surface of the wafer carrierbetween the wafer pockets. As illustrated in FIG. 5A, a cross-sectionalview of one embodiment, wafer carrier pocket 500 comprises base plate505 and top plate 510. As depicted, top plate 510 and wafer 515 aregenerally in the same horizontal plane and directly contact each other(e.g., FIGS. 5A, 5C, and 5E).

In a related embodiment, wafer 515 is situated to rest on the topsurface of tabs 520 located in certain locations along the periphery ofeach pocket 500. This arrangement is depicted in FIGS. 5C-5E. Tabs 520can be included to raise wafer 515 off of pocket floor surface 525 ofbase plate 505, thereby permitting some flow of gas around the edges andbelow the bottom surface of wafer 515. In related configurations, thedistance between base plate 505 and top plate 510 is equal to thedistance between base plate 505 and wafer 515.

As illustrated in FIG. 5E, similarly-sized tabs 520 can be formed, forexample, from extensions of base plate 505 to provide the same orsimilar spacing between top plate 510 and pocket floor surface 525 ofbase plate 505, as that between wafer 515 and pocket floor surface 525of base plate 505. Embodiments configured as such generally maintainsimilar heat flux in the wafer carrier body regions not covered bywafers (i.e., beneath the areas in the spaces between the wafers), asthose regions covered by wafers (i.e., wafer pockets).

In some aspects, a ring-shaped step can occupy the position of tabs 520(i.e., in lieu of tabs), such that the entire outer periphery of wafer515 rests on the ring-step. In other embodiments, as shown in FIGS. 5Band 5D, a portion of base plate 505 can extend upward and occupy aposition around the periphery of wafer 515, such that top plate 510 isgenerally in the same horizontal plane as wafer 515, but may notdirectly contact wafer 515. The portion of base plate 515 that extendsupward is situated between top plate 510 and wafer 515. In relatedconfigurations, the distance between base plate 505 and top plate 510 aswell as the distance between base plate 505 and wafer 515 can generallybe kept equal.

To create a more uniform temperature gradient across the surface ofwafer 515, a wafer carrier can be constructed such that top plate 510occupies the exposed portions of the wafer carrier (i.e., the areas notoccupied by wafers; see FIGS. 4 and 6). In various embodiments, topplate 510 can be comprised of the same material as wafer 515, have thesame thickness as wafer 515, and be the same distance from base plate505. For example, if wafer 515 is comprised of sapphire, then top plate510 will also be comprised of sapphire. If wafer 515 is comprised ofsilicon (Si), then top plate 510 will also be comprised of silicon (Si).Similarly, if wafer 515 is 500 microns thick, then top plate 510 willalso be 500 microns thick. Additionally, if wafer 515 is 50 microns frombase plate 505, then top plate will also be 50 microns from base plate505 (see, e.g., FIG. 5E), or if wafer 515 directly contacts base plate505, then top plate will also directly contact base plate 505 (see,e.g., FIGS. 5A and 5B). With respect to base plate 505 in suchembodiments, if wafer 515 and top plate 510 are comprised of silicon orsapphire, for example, base plate 505 can generally be comprised ofeither solid silicon carbide or silicon carbide-coated graphite. Invarious embodiments, the top plate is formed from a ceramic materialsuch as a material selected from among: quartz, solid silicon carbide,aluminum nitride, boron nitride, boron carbide, alumina or anotherrefractory material. The selection of ceramic material for the top platecan be made in conjunction with the thickness of the top plate, andgeometry of the wafer carrier's bottom plate and pocket geometry toproduce a thermal insulating effect that is equivalent to the thermalinsulating effect of the wafers situated in their respective pockets,thereby producing a uniform heat blanketing effect over the surface ofthe wafer carrier in operation. For instance, in still otherembodiments, a wafer comprising silicon can be used with a base platecomprising solid silicon carbide or silicon carbide coated graphite, anda top plate comprising silicon carbide or aluminum nitride. In stillother embodiments, top plate 510 can be constructed from materials thathave different thermal properties than wafer 515. The difference inthermal properties can be based on emissivity, coefficient of thermalexpansion (CTE), and/or thermal conductivity.

In the embodiment depicted in FIG. 5A, top plate 510 is constructed andsituated to form the peripheral walls of each wafer pocket. Theseperipheral walls will retain the wafers during processing. FIGS. 5B and5D illustrate other embodiments, in which the peripheral walls 506 foreach wafer pocket are formed by extensions of base plate 505. This typeof structure is illustrated in a perspective view in FIG. 6B. In suchembodiments, top plate or top plates 510 occupy the exposed areas of thewafer carrier (i.e., the areas not occupied by wafers), and theperipheral walls 506 of the extensions of base plate 505 will retainwafers 515 during processing. Therefore, in the cross-sectional views ofFIGS. 5B and 5D, the peripheral walls 506 of the extensions of baseplate 505 are located between wafer 515 and top plate 510. Exemplaryembodiments of such configurations are shown in FIG. 6C, wherein topplate 510 is composed of various segments.

In various embodiments, top plate 600 can be comprised of a single pieceof material that covers the exposed areas of the wafer carrier butleaves holes 605 for the wafers, as shown in FIG. 6A. In suchembodiments, top plate 600 surrounds each wafer, as well as the centerand outer periphery of the wafer carrier. Additionally, fasteningmechanisms can be used to connect top plate 600 to a base plate. Forexample, as shown in FIG. 6A, top plate 600 can be connected to a baseplate using wire staples 610. In some cases, wire staples 610 can becomprised of molybdenum, or other suitable metal or alloy.Advantageously, the use of staples or other fastening mechanismfacilitates removal of the top plate.

In another embodiment, the top plate is secured to the bottom plateusing sintering, a high-temperature adhesive, or other form of permanentbonding.

In other embodiments, top plate 600 can be comprised of multiple pieces,each having a shape corresponding to an exposed area of the wafercarrier, as shown in FIG. 6B. For example, top plate segments 615 cansurround the circumference of each wafer, as well as the center andouter periphery of the wafer carrier, but do not physically connect toother top plate segments 615. In various embodiments, top plate 600 ortop plate segments 615 can be comprised of the same material as thewafers, have the same thickness as the wafers, and be the same distancefrom base plate, in order to reduce temperature non-uniformities. Inrelated embodiments, the material between the top plate and the wafersis different, while their relative thickness is correspondinglydifferent to produce an equivalent thermal insulating effect. Likewise,in another related type of embodiment, a difference between the spacingbetween the bottom plate and the wafer on the one hand, and the spacingbetween the bottom plate and the top plate on the other hand iscompensated by suitable variation in the material, the thickness, orboth properties, between the top plate and the wafers, so as to providea uniform thermal insulation characteristic over the surface of thewafer carrier.

As shown in FIGS. 7A through 7C (cross-sectional views of wafer carrierpocket 700), embodiments of a wafer carrier can comprise a base plate705 and top plate 710, such that wafer 715 is not situated to rest onany portion of base plate 705, including tabs or a ring structure ofbase plate 705. Instead, wafer 715 can be situated to rest directly onpocket floor surface 725 of pocket 700 created within top plate 710, asshown in FIG. 7A. In such configurations, peripheral walls 706 of waferpocket 700 are provided by top plate 710. Peripheral walls 706 willretain wafer 715 during processing. In related embodiments, as shown inFIG. 7B, wafer 715 can be situated to rest on the top surface of tabs720 extending outward from top plate 710. Tabs 720 can be located incertain locations along the periphery of each pocket 700, such that topplate 710 and wafer 715 are generally in the same horizontal plane anddirectly contact each other. Tabs 720 raise wafer 715 off pocket floorsurface 730 of base plate 705, thereby permitting some flow of gasaround the edges and below the bottom surface of wafer 715 (FIG. 7B).

In related embodiments, similarly-sized tabs 720 can be formed fromextensions of top plate 710 to provide the same or similar spacingbetween top plate 710 and floor surface 726 of base plate 705 in areasnot covered by wafers 715, as the spacing between pocket floor surface725 created within top plate 710 in areas covered by wafers 715 (FIG.7C). Embodiments configured as such maintain similar heat flux in thewafer carrier body regions not covered by wafers (i.e., beneath theareas in the spaces between the wafers), as those regions beneath thewafers (i.e., wafer pockets). As discussed above, top plate 700 can becomprised of a single piece of material that covers the exposed areas ofthe wafer carrier but leaves holes for wafers 715 (See FIG. 6A). Inother embodiments, top plate 700 can be comprised of multiple pieces,each having a shape corresponding to an exposed area of the wafercarrier (See FIG. 6B).

Tangential temperature gradient profiles obtained during MOCVDprocessing can indicate the presence and degree of temperaturenon-uniformities on the surface of wafers and on the exposed areas ofthe wafer carrier. For example, as shown in FIG. 8, the tangentialtemperature gradient profile indicates significant temperaturevariability on the surface of gallium nitride (GaN) wafers and exposedareas of the wafer carrier (right panels; “standard carrier”). However,the use of a wafer carrier comprising the top plate and base plateconfigurations described herein significantly reduces the temperaturevariability (left panels; “cover carrier”). Similar reductions intemperature variability are obtained using wafers with multiple quantumwells (MQW), as shown in the tangential temperature gradient profiles inFIG. 9A and the corresponding table summarizing the data in FIG. 9B. Insome embodiments, the use of a wafer carrier comprising the top plateand base plate configurations described herein can reduce temperaturevariability during CVD processing by a factor of about 2.0, 2.5, 3.0,3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 8.5, 9.0, 9.5, or 10.

The embodiments above are intended to be illustrative and not limiting.Other variations are contemplated to fall within the claims. Inaddition, although aspects of the present invention have been describedwith reference to particular embodiments, those skilled in the art willrecognize that changes can be made in form and detail without departingfrom the scope of the invention, as defined by the claims. Persons ofordinary skill in the relevant arts will recognize that the inventionmay comprise fewer features than illustrated in any individualembodiment described above. The embodiments described herein are notmeant to be an exhaustive presentation of the ways in which the variousfeatures of the invention may be combined. Accordingly, the embodimentsare not mutually exclusive combinations of features; rather, theinvention may comprise a combination of different individual featuresselected from different individual embodiments, limited only accordingto the appended claims.

Any incorporation by reference of documents above is limited such thatno subject matter is incorporated that is contrary to the explicitdisclosure herein. Any incorporation by reference of documents above isfurther limited such that no claims that are included in the documentsare incorporated by reference into the claims of the presentApplication. The claims of any of the documents are, however,incorporated as part of the disclosure herein, unless specificallyexcluded. Any incorporation by reference of documents above is yetfurther limited such that any definitions provided in the documents arenot incorporated by reference herein unless expressly included herein.

For purposes of interpreting the claims for the present invention, it isexpressly intended that the provisions of Section 112(f) of 35 U.S.C.are not to be invoked unless the specific terms “means for” or “stepfor” are recited in a claim.

1-16. (canceled)
 17. A method for reducing temperature non-uniformitiesaffecting a characteristic of a device formed in a chemical vapordeposition (CVD) tool, the method comprising: forming a base plate thatincludes surface portions arranged to support each of a plurality ofwafers, forming a top plate having a size and shape that fits overportions of the base plate that do not reside beneath any of theplurality of wafers; removably securing the top plate to the bottomplate to produce a relative arrangement of the base plate, top plate,and the plurality of wafers in which a more uniform thermal insulatingcharacteristic over the surface of each one of the plurality of wafersduring CVD processing is provided compared to an arrangement lacking thetop plate.
 18. The method of claim 17, wherein forming the top plateincludes forming a unitary member that includes a plurality of aperturessized and positioned to accept a the plurality of wafers.
 19. The methodof claim 17, wherein removably securing the top plate to the bottomplate includes securing the top plate and the bottom plate using aplurality of staples.
 20. The method of claim 17, wherein forming thetop plate includes forming a plurality of individual segments, each ofwhich is contoured to fit in a corresponding region over the top platebetween the plurality of wafers.